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74F38SJX PDF预览

74F38SJX

更新时间: 2024-11-26 23:24:07
品牌 Logo 应用领域
其他 - ETC
页数 文件大小 规格书
5页 62K
描述
Quad 2-input NAND Gate

74F38SJX 数据手册

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April 1988  
Revised November 1999  
74F38  
Quad Two-Input NAND Buffer (Open Collector)  
General Description  
This device contains four independent gates, each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F38SC  
74F38SJ  
74F38PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Unit Loading/Fan Out  
U.L.  
Input IIH/IIL  
Pin Names  
Description  
HIGH/LOW  
Output IOH/IOL  
An, Bn  
Inputs  
1.0/2.0  
20 µA/1.2 mA  
On  
Outputs  
OC (Note 1) /106.6  
OC (Note 1) /64 mA  
Note 1: OC = Open Collector  
Function Table  
Inputs  
Output  
A
L
B
L
O
H
H
H
L
L
H
L
H
H
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
© 1999 Fairchild Semiconductor Corporation  
DS009465  
www.fairchildsemi.com  

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