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74F395

更新时间： 2024-11-26 22:49:47
品牌 Logo 应用领域
恩智浦 - NXP 移位寄存器
页数 文件大小 规格书
7页 67K
描述
4-bit cascadable shift register 3-State

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74F395 数据手册

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Philips Semiconductors  
Product specification  
4-bit cascadable shift register (3-State)  
74F395  
FEATURES  
PIN CONFIGURATION  
• 4-bit parallel load shift register  
MR  
Ds  
D0  
D1  
D2  
1
2
3
4
5
16  
V
CC  
• Independent 3-State buffer outputs, Q0–Q3  
• Separate Qs output for serial expansion  
• Asynchronous Master Reset  
15 Q0  
14 Q1  
13 Q2  
12 Q3  
11 Qs  
10 CP  
D3  
6
DESCRIPTION  
The 74F395 is a 4-bit Shift Register with serial and parallel  
synchronous operating modes and 3-State buffer outputs. The  
shifting and loading operations are controlled by the state of the  
Parallel Enable (PE) input. When PE is High, data is loaded from the  
Parallel Data inputs (D0–D3) into the register synchronous with the  
High-to-Low transition of the Clock input (CP). When PE is Low, the  
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and  
the data in the register is shifted one bit to the right in the direction  
(Q0! Q1! Q2! Q3) synchronous with the negative clock transition.  
The PE and Data inputs are fully edge-triggered and must be stable  
one setup prior to the High-to-Low transition of the clock.  
PE  
7
8
GND  
9
OE  
SF00940  
TYPICAL SUPPLY CURRENT  
(TOTAL)  
TYPE  
TYPICAL f  
MAX  
74F395  
120MHz  
32mA  
ORDERING INFORMATION  
The Master Reset (MR) is an asynchronous active-Low input. When  
Low, the MR overrides the clock and all other inputs and clears the  
register.  
COMMERCIAL RANGE  
DESCRIPTION  
V
CC  
= 5V ±10%, T  
= 0°C to +70°C  
amb  
The 3-state output buffers are designed to drive heavily loaded  
3-State buses, or large capacitive loads.  
16-pin plastic DIP  
16-pin plastic SO  
N74F395N  
N74F395D  
The active-Low Output Enable (OE) controls all four 3-State buffers  
independent of the register operation. The data in the register  
appears at the outputs when OE is Low. The outputs are in High  
impedance “OFF” state, which means they will neither drive nor load  
the bus when OE is High. The output from the last stage is brought  
out separately. This output (Qs) is tied to the Serial Data input (Ds)  
of the next register for serial expansion applications. The Qs output  
is not affected by the 3-State buffer operation.  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
LOAD VALUE  
74F (U.L.)  
HIGH/LOW  
PINS  
DESCRIPTION  
HIGH/LOW  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
1.0mA/20mA  
3.0mA/24mA  
D0 – D3  
Ds  
Data inputs  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33  
Serial data input  
Parallel Enable input  
PE  
MR  
Master Reset input (active Low)  
Output Enable input (active Low)  
Clock Pulse input (active falling edge)  
Serial expansion output  
OE  
CP  
Qs  
Q0–Q3  
Data outputs (3-State)  
150/40  
NOTE:  
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.  
1
1990 Oct 23  
853–0370 00780  
1234567

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