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74F379SCQR PDF预览

74F379SCQR

更新时间: 2024-11-01 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 59K
描述
D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, TTL, PDSO16, 0.150 INCH, SOIC-16

74F379SCQR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65其他特性:WITH HOLD MODE
系列:F/FASTJESD-30 代码:R-PDSO-G16
长度:9.9 mm逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:140 MHzBase Number Matches:1

74F379SCQR 数据手册

 浏览型号74F379SCQR的Datasheet PDF文件第2页浏览型号74F379SCQR的Datasheet PDF文件第3页浏览型号74F379SCQR的Datasheet PDF文件第4页浏览型号74F379SCQR的Datasheet PDF文件第5页浏览型号74F379SCQR的Datasheet PDF文件第6页 
May 1988  
Revised August 1999  
74F379  
Quad Parallel Register with Enable  
General Description  
The 74F379 is a 4-bit register with buffered common  
Enable. This device is similar to the 74F175 but features  
the common Enable rather than common Master Reset.  
Features  
Edge triggered D-type inputs  
Buffered positive edge-triggered clock  
Buffered common enable input  
True and complement outputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74F379SC  
74F379SJ  
74F379PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009527  
www.fairchildsemi.com  

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