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74F193PCQR PDF预览

74F193PCQR

更新时间: 2024-11-09 12:57:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
7页 74K
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74F193PCQR 数据手册

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April 1988  
Revised July 1999  
74F193  
Up/Down Binary Counter with Separate Up/Down Clocks  
that are used as the clocks for subsequent stages without  
extra logic, thus simplifying multi-stage counter designs.  
General Description  
The 74F193 is an up/down modulo-16 binary counter. Sep-  
Individual preset inputs allow the circuit to be used as a  
arate Count Up and Count Down Clocks are used, and in  
programmable counter. Both the Parallel Load (PL) and the  
either counting mode the circuits operate synchronously.  
Master Reset (MR) inputs asynchronously override the  
The outputs change state synchronously with the LOW-to-  
clocks.  
HIGH transitions on the clock inputs. Separate Terminal  
Count Up and Terminal Count Down outputs are provided  
Ordering Code:  
Order Number Package Number  
Package Description  
74F193SC  
74F193SJ  
74F193PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009497  
www.fairchildsemi.com  

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