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74CBTLV3861DK,118 PDF预览

74CBTLV3861DK,118

更新时间: 2024-12-02 10:45:07
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
18页 158K
描述
74CBTLV3861 - 10-bit bus switch with output enable SSOP2 24-Pin

74CBTLV3861DK,118 数据手册

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74CBTLV3861  
10-bit bus switch with output enable  
Rev. 3 — 16 December 2011  
Product data sheet  
1. General description  
The 74CBTLV3861 is a 10-bit bus switch with one output enable (OE) input. When OE is  
LOW, the switch is closed and port A is connected to the B port. When OE is HIGH, the  
switch is disabled.  
To ensure the high-impedance OFF-state during power-up or power-down, OE should be  
tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined  
by the current-sinking capability of the driver.  
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 2.3 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Supply voltage range from 2.3 V to 3.6 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM AEC-Q100-011 revision B exceeds 1000 V  
5 switch connection between two ports  
Rail to rail switching on data I/O ports  
CMOS low power consumption  
Latch-up performance exceeds 250 mA per JESD78B Class I level A  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  

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