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74AVCH8T245PW:118 PDF预览

74AVCH8T245PW:118

更新时间： 2024-11-29 15:46:47
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恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
24页 119K
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74AVCH8T245 - 8-bit dual supply translating transceiver TSSOP2 24-Pin

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74AVCH8T245PW:118 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP2包装说明：4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.75
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：AVCJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
负载电容（CL）：15 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.006 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：9.9 ns传播延迟（tpd）：9.9 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.1 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
翻译：1.5/3.3V &1.5/3.3V宽度：4.4 mm
Base Number Matches：1

74AVCH8T245PW:118 数据手册

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74AVCH8T245  
8-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 02 — 28 April 2009  
Product data sheet  
1. General description  
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level  
translation. It features two data input-output ports (An and Bn), a direction control input  
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)  
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device  
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,  
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are  
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on  
DIR allows transmission from B to A. The output enable input (OE) can be used to disable  
the outputs so the buses are effectively isolated.  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold  
circuitry on the powered-up side always stays active.  
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or  
floating data inputs at a valid logic level. This feature eliminates the need for external  
pull-up or pull-down resistors.  
2. Features  
I Wide supply voltage range:  
N VCC(A): 0.8 V to 3.6 V  
N VCC(B): 0.8 V to 3.6 V  
I Complies with JEDEC standards:  
N JESD8-12 (0.8 V to 1.3 V)  
N JESD8-11 (0.9 V to 1.65 V)  
N JESD8-7 (1.2 V to 1.95 V)  
N JESD8-5 (1.8 V to 2.7 V)  
N JESD8-B (2.7 V to 3.6 V)  
I ESD protection:  
N HBM JESD22-A114E Class 3B exceeds 8000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Maximum data rates:  
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)  
N 260 Mbit/s (≥ 1.1 V to 3.3 V translation)  
 
 
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74AVCH8T245PW:118 替代型号

型号 品牌 替代类型 描述 数据表
74AVCH8T245PW,112 NXP

完全替代

 74AVCH8T245 - 8-bit dual supply translating transceiver TSSOP2 24-Pin

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