Datasheet > 74AVCH2T45DC,125

74AVCH2T45DC,125

更新时间： 2025-09-25 19:14:43

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
27页	295K
描述
输出电压类型:三态，非反相 ;单电路的通道数(channel):2 ;VCCA最小值(V):0.8 V;VCCA最大值(V):3.6 V;VCCB最小值(V):0.8 V;VCCB最大值(V):3.6 V;通道方向类型:双向 ;元器件封装:8-VSSOP;

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74AVCH2T45DC,125 技术参数

生命周期：	Active	零件包装代码：	SSOP
包装说明：	VSSOP,	针数：	8
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	0.74	系列：	AVC
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e4
长度：	2.3 mm	逻辑集成电路类型：	BUS TRANSCEIVER
湿度敏感等级：	1	位数：	2
功能数量：	1	端口数量：	2
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	VSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	9.9 ns	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	0.8 V
标称供电电压 (Vsup)：	1.1 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	2 mm
Base Number Matches：	1

74AVCH2T45DC,125 数据手册

74AVCH2T45

Dual-bit, dual-supply voltage level translator/transceiver;

3-state

Rev. 7 — 20 February 2018

Product data sheet

1 General description

The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level

translation. It features two data input-output ports (nA and nB), a direction control input

(DIR) and dual supply pins (V_CC(A)and V_CC(B)). Both V_CC(A)and V_CC(B)can be supplied at

any voltage between 0.8 V and 3.6 V making the device suitable for translating between

any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and

DIR are referenced to V_CC(A)and pins nB are referenced to V_CC(B). A HIGH on DIR

allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both A and B are in the high-impedance OFF-state.

The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2 Features and benefits

• Wide supply voltage range:

– V_CC(A): 0.8 V to 3.6 V

– V_CC(B): 0.8 V to 3.6 V

• High noise immunity

• Complies with JEDEC standards:

– JESD8-12 (0.8 V to 1.3 V)

– JESD8-11 (0.9 V to 1.65 V)

– JESD8-7 (1.2 V to 1.95 V)

– JESD8-5 (1.8 V to 2.7 V)

– JESD8-B (2.7 V to 3.6 V)

• ESD protection:

– HBM JESD22-A114F Class 3B exceeds 8000 V

– MM JESD22-A115-A exceeds 200 V

– CDM JESD22-C101C exceeds 1000 V

• Maximum data rates:

– 500 Mbps (1.8 V to 3.3 V translation)

– 320 Mbps (< 1.8 V to 3.3 V translation)

– 320 Mbps (translate to 2.5 V or 1.8 V)

– 280 Mbps (translate to 1.5 V)

– 240 Mbps (translate to 1.2 V)

• Suspend mode

• Bus hold on data inputs

12 3 4 5 6 7...27

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