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74AVC8T245PW PDF预览

74AVC8T245PW

更新时间： 2024-11-20 11:10:07
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
24页 333K
描述
8-bit dual supply translating transceiver with configurable voltage translation; 3-stateProduction

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74AVC8T245PW 技术参数

是否Rohs认证：符合生命周期：Active
包装说明：TSSOP-24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.6
Is Samacsys：N系列：AVC
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm逻辑集成电路类型：BUS TRANSCEIVER
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：9.9 ns
座面最大高度：1.1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

74AVC8T245PW 数据手册

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74AVC8T245  
8-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 7 — 29 April 2021  
Product data sheet  
1. General description  
The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It  
features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable  
input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any  
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low  
voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to  
VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and  
a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to  
disable the outputs so the buses are effectively isolated.  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing any damaging backflow current through the device when it is  
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn  
are in the high-impedance OFF-state.  
2. Features and benefits  
•
Wide supply voltage range:  
•
•
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
•
Complies with JEDEC standards:  
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
•
•
ESD protection:  
•
•
•
HBM JESD22-A114E Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
•
•
•
•
•
•
380 Mbit/s (≥ 1.8 V to 3.3 V translation)  
260 Mbit/s (≥ 1.1 V to 3.3 V translation)  
260 Mbit/s (≥ 1.1 V to 2.5 V translation)  
210 Mbit/s (≥ 1.1 V to 1.8 V translation)  
150 Mbit/s (≥ 1.1 V to 1.5 V translation)  
100 Mbit/s (≥ 1.1 V to 1.2 V translation)  
•
•
•
•
•
•
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 
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74AVC8T245PW 替代型号

型号 品牌 替代类型 描述 数据表
SN74AVC8T245QPWRQ1 TI

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