Datasheet > 74AVC4T774

74AVC4T774

更新时间： 2024-11-20 01:14:39

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
26页	281K
描述
4-bit dual supply translating transceiver 3-state

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AVC4T774 数据手册

74AVC4T774

4-bit dual supply translating transceiver; 3-state

Rev. 1 — 25 September 2017

Product data sheet

1 General description

The 74AVC4T774 is a 4-bit, dual supply transceiver that enables bidirectional level

translation. It features eight 1-bit input-output ports (An and Bn), four direction control

inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins

(V_CC(A)and V_CC(B)). Both V_CC(A)and V_CC(B)can be supplied at any voltage between

0.8 V and 3.6 V making the device suitable for translating between any of the low voltage

nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced

to V_CC(A)and pins Bn are referenced to V_CC(B). A HIGH on DIRn allows transmission from

An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input

(OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both An and Bn are in the high-impedance OFF-state.

2 Features and benefits

• Wide supply voltage range:

– V_CC(A): 0.8 V to 3.6 V

– V_CC(B): 0.8 V to 3.6 V

• Complies with JEDEC standards:

– JESD8-12 (0.8 V to 1.3 V)

– JESD8-11 (0.9 V to 1.65 V)

– JESD8-7 (1.2 V to 1.95 V)

– JESD8-5 (1.8 V to 2.7 V)

– JESD8-B (2.7 V to 3.6 V)

• ESD protection:

– HBM JESD22-A114E Class 3B exceeds 8000 V

– CDM JESD22-C101C exceeds 1500 V

• Maximum data rates:

– 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

– 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

– 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

– 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

– 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

– 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

• Suspend mode

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Inputs accept voltages up to 3.6 V

• I_OFFcircuitry provides partial Power-down mode operation

12 3 4 5 6 7...26

中文翻译

下载PDF

与74AVC4T774相关器件

型号	品牌	获取价格	描述	数据表
74AVC4T774BQ	NEXPERIA	获取价格	4-bit dual supply translating transceiver 3-state
74AVC4T774BQ-Q100	NEXPERIA	获取价格	4-bit dual supply translating transceiver; 3-stateProduction
74AVC4T774GU	NEXPERIA	获取价格	4-bit dual supply translating transceiver 3-state
74AVC4T774GU-Q100	NEXPERIA	获取价格	4-bit dual supply translating transceiver; 3-stateProduction
74AVC4T774PW	NEXPERIA	获取价格	4-bit dual supply translating transceiver; 3-stateProduction
74AVC4T774PW-Q100	NEXPERIA	获取价格	4-bit dual supply translating transceiver; 3-stateProduction
74AVC4T774RGYRG4	TI	获取价格	4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
74AVC4T774RSVRG4	TI	获取价格	4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
74AVC4T774RSVR-NT	TI	获取价格	4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Out
74AVC4TD245BQ	NEXPERIA	获取价格	4-bit dual supply translating transceiver with configurable voltage translation; 3-statePr

与74AVC4T774相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

22
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

14
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

44
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

43

产品中心

服务支持

精选活动

关于我们

帮助中心

74AVC4T774

74AVC4T774 数据手册

与74AVC4T774相关器件

与74AVC4T774相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74AVC4T774

74AVC4T774 数据手册

与74AVC4T774相关器件

与74AVC4T774相关文章

您还可以找

您在本页遇到什么问题？