Datasheet > 74AUP1T02GW

74AUP1T02GW

更新时间： 2023-09-03 20:37:32

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	231K
描述
Low-power 2-input NOR gate with voltage-level translatorProduction

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74AUP1T02GW 数据手册

Nexperia

74AUP1T02

Low-power 2-input NOR gate with voltage-level translator

11.1. Waveforms and test circuit

A, B input

GND

PHL

PLH

Y output

mna612

Measurement points are given in Table 9.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 4. Input A and B to output Y propagation delay times

Table 9. Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

2.3 V to 3.6 V

0.5 × V_CC

0.5 × V_I

1.65 V to 3.6 V

≤ 3.0 ns

EXT

5 kΩ

DUT

001aac521

Test data is given in Table 10.

Definitions for test circuit:

R_L= Load resistance;

C_L= Load capacitance including jig and probe capacitance;

R_T= Termination resistance should be equal to the output impedance Z_Oof the pulse generator;

V_EXT= External voltage for measuring switching times.

Fig. 5. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

V_CC

Load

V_EXT

C_L

R_L[1]

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

2.3 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

5 kΩ or 1 MΩ

GND

2 × V_CC

[1] For measuring enable and disable times R_L= 5 kΩ.

For measuring propagation delays, setup and hold times and pulse width R_L= 1 MΩ.

74AUP1T02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 21 July 2023

8 / 13

1...5 6 789 10 11...13

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