Datasheet > 74AUP1T02GW

74AUP1T02GW

更新时间： 2023-09-03 20:37:32

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	231K
描述
Low-power 2-input NOR gate with voltage-level translatorProduction

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74AUP1T02GW 数据手册

Nexperia

74AUP1T02

Low-power 2-input NOR gate with voltage-level translator

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Marking..........................................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................2

6.1. Pinning.........................................................................2

6.2. Pin description.............................................................2

7. Functional description................................................. 3

8. Limiting values............................................................. 3

9. Recommended operating conditions..........................3

10. Static characteristics..................................................4

11. Dynamic characteristics.............................................6

11.1. Waveforms and test circuit........................................ 8

12. Package outline.......................................................... 9

13. Abbreviations............................................................11

14. Revision history........................................................11

15. Legal information......................................................12

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 21 July 2023

74AUP1T02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 21 July 2023

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