Datasheet > 74AUP1T02GW

74AUP1T02GW

更新时间： 2023-09-03 20:37:32

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	231K
描述
Low-power 2-input NOR gate with voltage-level translatorProduction

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74AUP1T02GW 数据手册

Nexperia

74AUP1T02

Low-power 2-input NOR gate with voltage-level translator

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

V_CC= 2.3 V to 2.7 V; V_I= 2.3 V to 2.7 V

t_pd

propagation

delay

A, B to Y; see Fig. 4

C_L= 5 pF

[2]

1.5

2.0

2.4

3.4

3.2

3.8

4.2

5.4

5.1

5.8

6.4

7.7

0.5

1.0

1.5

6.0

7.1

0.5

1.0

1.5

6.6

7.9

8.7

C_L= 10 pF

C_L= 15 pF

7.9

C_L= 30 pF

10.0

11.0 ns

V_CC= 2.3 V to 2.7 V; V_I= 3.0 V to 3.6 V

t_pd

propagation

delay

A, B to Y; see Fig. 4

C_L= 5 pF

1.2

1.7

2.0

3.1

2.9

3.5

4.0

5.2

4.7

5.4

6.0

7.4

0.5

1.0

1.5

5.5

6.5

7.4

9.5

0.5

1.0

1.5

6.1

7.2

8.2

C_L= 10 pF

C_L= 15 pF

C_L= 30 pF

10.5 ns

V_CC= 3.0 V to 3.6 V; V_I= 1.65 V to 1.95 V

t_pd

propagation

delay

A, B to Y; see Fig. 4

C_L= 5 pF

1.9

2.0

2.7

3.5

2.8

3.3

3.8

4.9

4.0

4.5

5.1

6.6

0.5

1.0

1.5

8.0

8.5

9.1

9.8

0.5

1.0

1.5

8.8

9.4

C_L= 10 pF

C_L= 15 pF

10.1 ns

10.8 ns

C_L= 30 pF

V_CC= 3.0 V to 3.6 V; V_I= 2.3 V to 2.7 V

t_pd

propagation

delay

A, B to Y; see Fig. 4

C_L= 5 pF

1.4

1.9

2.4

3.3

2.7

3.2

3.7

4.9

4.1

4.8

5.4

6.7

0.5

1.0

1.5

5.3

6.1

6.8

8.5

0.5

1.0

1.5

5.9

6.8

7.5

9.4

C_L= 10 pF

C_L= 15 pF

C_L= 30 pF

V_CC= 3.0 V to 3.6 V; V_I= 3.0 V to 3.6 V

t_pd

propagation

delay

A, B to Y; see Fig. 4

C_L= 5 pF

1.1

1.6

2.0

3.0

2.6

3.2

3.6

4.8

4.2

4.9

5.5

6.8

0.5

1.0

1.5

4.7

5.7

6.2

7.8

0.5

1.0

1.5

5.2

6.3

6.9

8.6

C_L= 10 pF

C_L= 15 pF

C_L= 30 pF

T_amb= 25 °C

C_PDpower

f_i= 1 MHz; V_I= GND to V_CC[3]

V_CC= 2.3 V to 2.7 V

dissipation

capacitance

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AUP1T02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 21 July 2023

7 / 13

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