Datasheet > 74AUP1G0832GN

74AUP1G0832GN

更新时间： 2023-09-03 20:29:55

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
16页	258K
描述
Low-power 3-input AND-OR gateProduction

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中文翻译

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数据手册

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74AUP1G0832GN 数据手册

Nexperia

74AUP1G0832

Low-power 3-input AND-OR gate

Symbol Parameter

C_L= 15 pF

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_pd

propagation A, B or C to Y; see Fig. 6

[2]

[3]

delay

V_CC= 0.8 V

26.6

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.2

2.5

2.3

2.1

1.9

7.3 14.2

2.8

2.6

2.0

1.9

1.8

14.7

9.1

7.5

5.6

4.8

2.8

2.6

2.0

1.9

1.8

16.2

10.0

8.3

5.1

4.2

3.4

3.2

8.3

6.7

5.0

4.5

6.2

5.3

C_L= 30 pF

t_pdpropagation A, B or C to Y; see Fig. 6

delay

V_CC= 0.8 V

34.8

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

4.1

3.3

3.0

2.8

2.6

9.5 19.0

6.6 11.0

3.6

3.3

2.6

2.5

2.4

19.8

12.1

10.0

7.4

3.6

3.3

2.6

2.5

2.4

21.8

13.3

11.0

8.3

5.5

4.5

4.3

8.8

6.6

5.9

6.4

7.0

T_amb= 25 °C

C_PDpower

f_i= 1 MHz;

dissipation

V_I= GND to V_CC

capacitance

V_CC= 0.8 V

2.5

2.7

2.8

2.9

3.4

4.0

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AUP1G0832

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 13 July 2023

8 / 16

1...5 6 789 10 11...16

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