Datasheet > 74ALVT16501DL,118

74ALVT16501DL,118

更新时间： 2024-11-13 14:50:59

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恩智浦 - NXP		/
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20页	101K
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74ALVT16501

18-bit universal bus transceiver; 3-state

Rev. 04 — 8 August 2005

Product data sheet

1. General description

The 74ALVT16501 is a high-performance Bipolar Complementary Metal Oxide

Semiconductor (BiCMOS) product designed for V_CCoperation at 2.5 V and 3.3 V with

I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring

non-inverting 3-state bus compatible outputs in both send and receive directions.

Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable

(LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.

If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the LOW-to-HIGH

transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the

outputs are in the high-impedance state.

Active bus hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

2. Features

■ 18-bit bidirectional bus interface

■ 5 V I/O compatible

■ 3-state buffers

■ Output capability: +64 mA to −32 mA

■ TTL and LVTTL input and output switching levels

■ Bus hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

■ Live insertion and extraction permitted

■ Power-up reset

■ Power-up 3-state

■ No bus current loading when output is tied to 5 V bus

■ Positive-edge triggered clock inputs

■ Latch-up protection:

◆ JESD78: exceeds 500 mA

■ ESD protection:

◆ MIL STD 883, method 3015: exceeds 2000 V

◆ Machine model: exceeds 400 V

12 3 4 5 6 7...20

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