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Datasheet > 74ALVCHR16543PA
74ALVCHR16543PA PDF预览

74ALVCHR16543PA

更新时间： 2024-02-14 23:21:30
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 85K
描述
TSSOP-56, Tube

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中文翻译

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74ALVCHR16543PA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.92其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240电源：3.3 V
Prop。Delay @ Nom-Sup：4.9 ns传播延迟（tpd）：6.9 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：6.1 mm
Base Number Matches：1

74ALVCHR16543PA 数据手册

 浏览型号74ALVCHR16543PA的Datasheet PDF文件第2页浏览型号74ALVCHR16543PA的Datasheet PDF文件第3页浏览型号74ALVCHR16543PA的Datasheet PDF文件第4页浏览型号74ALVCHR16543PA的Datasheet PDF文件第5页浏览型号74ALVCHR16543PA的Datasheet PDF文件第6页浏览型号74ALVCHR16543PA的Datasheet PDF文件第7页 
3.3V CMOS 16-BIT REGIS-  
TERED TRANSCEIVER WITH  
IDT74ALVCHR16543  
3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
This 16-bit registered transceiver is built using advanced dual metal  
CMOS technology. The ALVCHR16543 can be used as two 8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or  
LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow. The  
A-to-B enable (CEAB) input must be low to enter data from A or to output  
data from B. If CEAB is low and LEAB is low, the A-to-B latches are  
transparent; a subsequent low-to-high transition of LEAB puts the A  
latches in the storage mode. With CEAB and OEAB both low, the 3-state  
B outputs are active and reflect the data present at the output of the A  
latches. Data flow from B to A is similar, but requires using CEBA, LEBA,  
and OEBA.  
–
–
–
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.40mm pitch TVSOP package  
Extended commercial range of – 40°C to +85°C  
VCC = 3.3V ±0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ±0.2V  
CMOS power levels (0.4µW typ. static)  
–
–
–
–
–
–
–
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCHR16543:  
–
–
Balanced Output Drivers: ±12mA  
Low switching noise  
The ALVCHR16543 has series resistors in the device output struc-  
ture which will significantly reduce line noise when used with light loads.  
This driver has been designed to drive ±12mA at the designated  
threshold levels.  
The ALVCHR16543 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents  
floating inputs and eliminates the need for pull-up/down resistors.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
FUNCTIONAL BLOCK DIAGRAM  
56  
29  
1OEBA  
2OEBA  
2CEBA  
54  
31  
30  
28  
26  
1CEBA  
55  
LEBA  
OEAB  
CEAB  
LEBA  
2
OEAB  
2
CEAB  
2
1
1
1
1
3
2
27  
15  
1LEAB  
1A1  
2LEAB  
2A1  
C1  
1D  
C1  
1D  
5
42  
52  
1B1  
2B1  
C1  
1D  
C1  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
APRIL 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4946/-  
1234567

中文翻译

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