Datasheet > 74ALVCHR16543PV8

74ALVCHR16543PV8

更新时间： 2023-01-03 05:13:05

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
7页	85K
描述
SSOP-56, Reel

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74ALVCHR16543PV8 数据手册

IDT74ALVCHR16543

3.3V CMOS 16-BIT REGISTERED TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

3.3V CMOS 16-BIT REGIS-

TERED TRANSCEIVER WITH

IDT74ALVCHR16543

3-STATE OUTPUTS

AND BUS-HOLD

FEATURES:

DESCRIPTION:

This 16-bit registered transceiver is built using advanced dual metal

CMOS technology. The ALVCHR16543 can be used as two 8-bit

transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or

LEBA) and output-enable (OEAB or OEBA) inputs are provided for each

A-to-B enable (CEAB) input must be low to enter data from A or to output

data from B. If CEAB is low and LEAB is low, the A-to-B latches are

transparent; a subsequent low-to-high transition of LEAB puts the A

latches in the storage mode. With CEAB and OEAB both low, the 3-state

B outputs are active and reflect the data present at the output of the A

latches. Data flow from B to A is similar, but requires using CEBA, LEBA,

and OEBA.

–

0.5 MICRON CMOS Technology

Typical t^SK(0)(Output Skew) < 250ps

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

0.40mm pitch TVSOP package

Extended commercial range of – 40°C to +85°C

V^CC= 3.3V ±0.3V, Normal Range

V^CC= 2.7V to 3.6V, Extended Range

V^CC= 2.5V ±0.2V

CMOS power levels (0.4µW typ. static)

–

Rail-to-Rail output swing for increased noise margin

Drive Features for ALVCHR16543:

–

Balanced Output Drivers: ±12mA

Low switching noise

The ALVCHR16543 has series resistors in the device output struc-

ture which will significantly reduce line noise when used with light loads.

This driver has been designed to drive ±12mA at the designated

threshold levels.

The ALVCHR16543 has “bus-hold” which retains the inputs’ last state

whenever the input bus goes to a high impedance. This prevents

floating inputs and eliminates the need for pull-up/down resistors.

APPLICATIONS:

• 3.3V High Speed Systems

• 3.3V and lower voltage computing systems

FUNCTIONAL BLOCK DIAGRAM

1OEBA

2OEBA

2CEBA

1CEBA

LEBA

OEAB

CEAB

LEBA

OEAB

CEAB

1LEAB

1A1

2LEAB

2A1

1B1

2B1

TO SEVEN OTHER CHANNELS

EXTENDED COMMERCIAL TEMPERATURE RANGE

APRIL 1999

1999 Integrated Device Technology, Inc.

DSC-4946/-

12 3 4 5 6 7

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