Datasheet > 逻辑 > 总线驱动器/收发器> 74ALVCR162601TX

74ALVCR162601TX

更新时间： 2024-09-15 23:24:07

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
6页	94K
描述
18-Bit Bus Transceiver

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数据手册

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74ALVCR162601TX 数据手册

September 2001

Revised October 2001

74ALVCR162601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

and 26Ω Series Resistors in the Outputs

General Description

The 74ALVCR162601, 18-bit universal bus transceiver,

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched, and clocked modes.

Features

I 1.65–3.6V V_CCsupply operation

I 3.6V tolerant inputs and outputs

I 26Ω series resistors on both the A and B Port outputs.

I t_PD(A to B, B to A)

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the high-impedance state.

4.3 ns max for 3.0V to 3.6V V_CC

5.1 ns max for 2.3V to 2.7V V_CC

9.2 ns max for 1.65V to 1.95V V_CC

I Power-down HIGH impedance inputs and outputs

I Supports live insertion/withdrawal (Note 1)

I Uses patented noise/EMI reduction circuitry

I Latchup conforms to JEDEC JED78

I ESD performance:

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

Human body model > 2000V

The 74ALVCR162601 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O compatibility up to 3.6V.

Machine model >200V

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

The 74ALVCR162601 is also designed with 26Ω series

resistors on both the A and B Port outputs. This design

reduces line noise in applications such as memory address

drivers, clock drivers, and bus transceivers/transmitters.

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Package

Order Number

Package Description

Number

74ALVCR162601T

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS500660

www.fairchildsemi.com

12 3 4 5 6

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74ALVT162240DGG	NXP	获取价格	16-bit inverting buffer/driver with 30ohm termination resistors (3-State)
74ALVT162240DGG:11	NXP	获取价格	74ALVT162240 - 16-bit inverting buffer/driver with 30 Ohm termination resistors (3-State)
74ALVT162240DGG-T	NXP	获取价格	IC ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, Bus Driver/Transceiver
74ALVT162240DG-T	NXP	获取价格	IC ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, Bus Driver/Transceiver
74ALVT162240DL	NXP	获取价格	16-bit inverting buffer/driver with 30ohm termination resistors (3-State)
74ALVT162240DL,112	NXP	获取价格	74ALVT162240 - 16-bit inverting buffer/driver with 30 Ohm termination resistors (3-State)
74ALVT162240DL,118	NXP	获取价格	74ALVT162240 - 16-bit inverting buffer/driver with 30 Ohm termination resistors (3-State)
74ALVT162240DL-T	ETC	获取价格	Quad 4-Bit Buffer/Driver
74ALVT162241	NXP	获取价格	2.5V/3.3V 16-bit buffer/driver with 30ohm termination resistors 3-State

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