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74AHC1G126DCKRG4 PDF预览

74AHC1G126DCKRG4

更新时间: 2024-11-18 19:48:59
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 961K
描述
Single Bus Buffer Gate With 3-State Outputs 5-SC70 -40 to 125

74AHC1G126DCKRG4 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:SOIC包装说明:TSSOP, TSSOP5/6,.08
针数:5Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:0.89
控制类型:ENABLE HIGH计数方向:UNIDIRECTIONAL
系列:AHC/VHC/H/U/VJESD-30 代码:R-PDSO-G5
JESD-609代码:e4长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:2/5.5 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:1.25 mmBase Number Matches:1

74AHC1G126DCKRG4 数据手册

 浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第2页浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第3页浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第4页浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第5页浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第6页浏览型号74AHC1G126DCKRG4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢉ ꢊ  
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢎꢏꢀ ꢎꢏꢐ ꢐ ꢍ ꢑ ꢈ ꢄꢒꢍ  
ꢓ ꢋꢒ ꢅ ꢔ ꢕꢀꢒꢄꢒ ꢍ ꢖ ꢏꢒ ꢗꢏ ꢒ  
SCLS379J − AUGUST 1997 − REVISED JUNE 2005  
D
D
D
Operating Range of 2 V to 5.5 V  
D
D
8-mA Output Drive at 5 V  
Max t of 6 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
DCK PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
OE  
V
Y
1
2
3
5
1
2
3
5
OE  
A
V
Y
CC  
CC  
1
2
3
5
4
OE  
A
V
Y
CC  
A
4
GND  
4
GND  
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHC1G126 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the  
output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel of 4000  
SN74AHC1G126DBVR  
SN74AHC1G126DBVT  
SN74AHC1G126DCKR  
SN74AHC1G126DCKT  
SN74AHC1G126DRLR  
SOT (SOT-23) – DBV  
A26_  
−40°C to 85°C  
SOT (SC-70) – DCK  
AN_  
AN_  
SOT (SOT-553) – DRL  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)  
1
2
OE  
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢒꢤ  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AHC1G126DCKRG4 替代型号

型号 品牌 替代类型 描述 数据表
74AHC1G126DCKRE4 TI

完全替代

具有三态输出的单路 2V 至 5.5V 缓冲器 | DCK | 5 | -40 to 12
74AHC1G126DCKTG4 TI

完全替代

具有三态输出的单路 2V 至 5.5V 缓冲器 | DCK | 5 | -40 to 12
SN74AHC1G126DCKT TI

完全替代

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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