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74ACT520SJX PDF预览

74ACT520SJX

更新时间: 2024-11-08 23:24:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 运算电路逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 83K
描述
Identity Comparator

74ACT520SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, EIAJ TYPE2, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.66
Is Samacsys:N其他特性:WITH PULLUP RESISTORS ON B INPUTS; CASCADABLE
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
逻辑集成电路类型:IDENTITY COMPARATOR湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74ACT520SJX 数据手册

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February 1989  
Revised November 1999  
74AC520 74ACT520  
8-Bit Identity Comparator  
General Description  
Features  
Compares two 8-bit words in 6.5 ns typ  
Expandable to any word length  
20-pin package  
The AC/ACT520 are expandable 8-bit comparators. They  
compare two words of up to eight bits each and provide a  
LOW output when the two words match bit for bit. The  
expansion input IA = B also serves as an active LOW enable  
Outputs source/sink 24 mA  
ACT520 has TTL-compatible inputs  
input.  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC520SC  
74AC520PC  
74ACT520SC  
74ACT520SJ  
74ACT520PC  
M20B  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Word A Inputs  
Word B Inputs  
A0A7  
B0B7  
TA = B  
OA = B  
Expansion or Enable Input  
Identity Output  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010194  
www.fairchildsemi.com  

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