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74ACT374_01 PDF预览

74ACT374_01

更新时间: 2024-01-02 03:26:50
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
11页 238K
描述
OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED)

74ACT374_01 数据手册

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74ACT374  
OCTAL D-TYPE FLIP-FLOP  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED:  
= 260MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74ACT374B  
74ACT374M  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
74ACT374MTR  
74ACT374TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 374  
IMPROVED LATCH-UP IMMUNITY  
a normal logic state (high or low logic level); when  
the OE is high the outputs go to the high  
impedance state.  
DESCRIPTION  
The output control does not affect the internal  
operation of flip-flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74ACT374 is an advanced high-speed CMOS  
OCTAL D-TYPE FLIP-FLOP with 3 STATE  
OUTPUT NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type Flip-Flop are controlled by a  
clock input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
outputs will be set to the logic that were setup at  
the D inputs.  
While the (OE) input is low, the 8 outputs will be in  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

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