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74ACT374MTCX_NL PDF预览

74ACT374MTCX_NL

更新时间: 2024-02-14 09:53:10
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
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11页 238K
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74ACT374MTCX_NL 技术参数

生命周期:Contact Manufacturer包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
系列:ACTJESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):11 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

74ACT374MTCX_NL 数据手册

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74ACT374  
OCTAL D-TYPE FLIP-FLOP  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED:  
= 260MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74ACT374B  
74ACT374M  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
74ACT374MTR  
74ACT374TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 374  
IMPROVED LATCH-UP IMMUNITY  
a normal logic state (high or low logic level); when  
the OE is high the outputs go to the high  
impedance state.  
DESCRIPTION  
The output control does not affect the internal  
operation of flip-flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74ACT374 is an advanced high-speed CMOS  
OCTAL D-TYPE FLIP-FLOP with 3 STATE  
OUTPUT NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type Flip-Flop are controlled by a  
clock input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
outputs will be set to the logic that were setup at  
the D inputs.  
While the (OE) input is low, the 8 outputs will be in  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

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