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74ACT257MTR PDF预览

74ACT257MTR

更新时间: 2024-11-10 23:24:03
品牌 Logo 应用领域
其他 - ETC 复用器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 78K
描述
2-Input Digital Multiplexer

74ACT257MTR 数据手册

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74ACT257  
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)  
HIGH SPEED: t = 5 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT257B  
74ACT257M  
V
CC  
74ACT257MTR  
74ACT257TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 257  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
SELECT input is held LOW, ”A” data is selected;  
when SELECT input is held HIGH, ”B” data is  
selected.  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
DESCRIPTION  
The 74ACT257 is an advanced high-speed CMOS  
QUAD 2-CHANNEL MULTIPLEXER (3-STATE)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS tecnology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
It is composed of an independent 2-channel  
multiplexer with common SELECT and ENABLE  
(OE)inputs. It is a non-inverting multiplexer. When  
the ENABLE input is held HIGH, the outputs are  
forced to a high impedance state. When the  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

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