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74ACT11280DR PDF预览

74ACT11280DR

更新时间： 2024-11-21 12:58:11
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德州仪器 - TI /
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74ACT11280DR 数据手册

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SCAS046A − D3148, AUGUST 1988 − REVISED APRIL 1993  
54ACT11280 . . . J PACKAGE  
74ACT11280 . . . D OR N PACKAGE  
• Inputs Are TTL-Voltage Compatible  
• Generates Either Odd or Even Parity for  
(TOP VIEW)  
Nine Data Lines  
• Cascadable for n-Bits Parity  
B
A
C
D
E
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
• Flow-Through Architecture Optimizes  
Σ ODD  
GND  
Σ EVEN  
NC  
PCB Layout  
CC  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
F
G
H
• EPICt (Enhanced-Performance Implanted  
I
8
CMOS) 1-mm Process  
• 500-mA Typical Latch-Up Immunity  
at 125°C  
54ACT11280 . . . FK PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
3
2
1
20 19  
18  
G
C
NC  
B
4
5
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8
NC  
H
description  
17  
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15  
14  
These universal, monolithic, 9-bit parity  
generators/checkers feature odd and even  
outputs to facilitate operation of either an odd or  
NC  
I
NC  
A
9 10 11 12 13  
even parity application.  
The word-length  
capability is easily expanded by cascading.  
The 54ACT11280 is characterized for operation  
over the full military temperature range of − 55°C  
to 125°C. The 74ACT11280 is characterized for  
operation from − 40°C to 85°C.  
NC − No internal connection  
†
logic symbol  
FUNCTION TABLE  
NUMBER OF INPUTS  
A THRU I  
THAT ARE HIGH  
OUTPUTS  
2
A
2k  
S EVEN  
S ODD  
1
B
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
14  
C
H
13  
D
5
3
Σ EVEN  
Σ ODD  
12  
E
10  
F
9
G
8
H
7
I
†
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
12345

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