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74ACT11253J PDF预览

74ACT11253J

更新时间： 2024-11-18 13:04:51
品牌 Logo 应用领域
德州仪器 - TI 复用器输出元件
页数 文件大小 规格书
5页 80K
描述
IC,LOGIC MUX,DUAL,4-INPUT,ACT-CMOS,DIP,16PIN,CERAMIC

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74ACT11253J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：not_compliant
风险等级：5.86JESD-30 代码：R-XDIP-T16
逻辑集成电路类型：MULTIPLEXER功能数量：2
输入次数：4端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：CERAMIC
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified子类别：Multiplexer/Demultiplexers
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

74ACT11253J 数据手册

 浏览型号74ACT11253J的Datasheet PDF文件第2页浏览型号74ACT11253J的Datasheet PDF文件第3页浏览型号74ACT11253J的Datasheet PDF文件第4页浏览型号74ACT11253J的Datasheet PDF文件第5页 
54ACT11253, 74ACT11253  
DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS  
WITH 3-STATE OUTPUTS  
SCAS040A – D3110, MARCH 1988 – REVISED APRIL 1993  
• Inputs Are TTL-Voltage Compatible  
• 3-State Version of ′ACT11153  
54ACT11253 . . . J PACKAGE  
74ACT11253 . . . D OR N PACKAGE  
(TOP VIEW)  
• Permits Multiplexing From N Lines to  
One Line  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1C0  
1C1  
1C2  
1C3  
A
B
1Y  
GND  
2Y  
1G  
• Performs Parallel-to-Serial Conversion  
• Package Options Include Plastic Small-  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
V
CC  
2C0  
2C1  
2C2  
2G  
2C3  
• Flow-Through Architecture Optimizes  
PCB Layout  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
54ACT11253 . . . FK PACKAGE  
(TOP VIEW)  
• EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
description  
3
2
1
20 19  
18  
2C1  
2C2  
NC  
1C1  
1C0  
NC  
A
4
5
6
7
8
Each of these data selectors/multiplexers  
contains inverters and drivers to supply full binary  
decoding data selection to the AND-OR gates.  
Separate output control inputs are provided for  
each of the two four-line sections.  
17  
16  
15  
14  
2C3  
2G  
B
9 10 11 12 13  
The 3-state outputs can interface with and drive  
data lines of bus-organized systems. With all but  
one of the common outputs disabled (at a  
high-impedance state), the low-impedance of  
the single enabled output will drive the bus line  
to a high or low logic level. Each output has  
its own strobe (G). The outputs are disabled when  
G is high.  
NC – No internal connection  
†
logic symbol  
1
2
0
1
A
B
0
3
The 54ACT11253 is characterized for operation  
over the full military temperature range of – 55°C  
to 125°C. The 74ACT11253 is characterized for  
operation from – 40°C to 85°C.  
G
MUX  
6
1G  
1C0  
1C1  
1C2  
1C3  
2G  
EN  
0
16  
15  
14  
13  
7
FUNCTION TABLE  
SELECT  
OUTPUT  
3
5
DATA INPUTS  
OUTPUT  
Y
1
2
3
1Y  
2Y  
INPUTS  
CONTROL  
G
B
X
L
A
X
L
C0 C1 C2 C3  
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
11  
10  
9
L
L
H
X
X
X
X
X
X
H
L
2C0  
2C1  
2C2  
L
H
H
L
L
H
X
X
X
X
H
L
8
H
H
H
H
2C3  
L
H
X
X
H
L
†
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
H
H
H
H
Address inputs A and B are common to both sections.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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