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74ACT11253N PDF预览

74ACT11253N

更新时间: 2024-11-18 20:06:19
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路
页数 文件大小 规格书
5页 85K
描述
Multiplexer, ACT Series, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDIP16, PLASTIC, DIP-16

74ACT11253N 技术参数

生命周期:Contact Manufacturer包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.78其他特性:CENTER VCC/GND PINS
系列:ACTJESD-30 代码:R-PDIP-T16
长度:19.305 mm逻辑集成电路类型:MULTIPLEXER
功能数量:2输入次数:4
输出次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):14.3 ns座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

74ACT11253N 数据手册

 浏览型号74ACT11253N的Datasheet PDF文件第2页浏览型号74ACT11253N的Datasheet PDF文件第3页浏览型号74ACT11253N的Datasheet PDF文件第4页浏览型号74ACT11253N的Datasheet PDF文件第5页 
ꢋꢌꢂ ꢍꢉꢅ ꢎꢏ ꢐ ꢎꢁ ꢉꢋꢂꢄꢂꢉꢑ ꢒꢍ ꢒꢃꢄꢏ ꢓꢑꢔ ꢕꢌ ꢍꢄ ꢖ ꢗꢍ ꢒꢘ ꢒ ꢓ  
SCAS040A − D3110, MARCH 1988 − REVISED APRIL 1993  
Inputs Are TTL-Voltage Compatible  
3-State Version of ACT11153  
54ACT11253 . . . J PACKAGE  
74ACT11253 . . . D OR N PACKAGE  
(TOP VIEW)  
Permits Multiplexing From N Lines to  
One Line  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1C0  
1C1  
1C2  
1C3  
A
B
1Y  
GND  
2Y  
1G  
Performs Parallel-to-Serial Conversion  
Package Options Include Plastic Small-  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
V
CC  
2C0  
2C1  
2C2  
2G  
2C3  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
54ACT11253 . . . FK PACKAGE  
(TOP VIEW)  
EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
description  
3
2
1
20 19  
18  
2C1  
2C2  
NC  
1C1  
1C0  
NC  
A
4
5
6
7
8
Each of these data selectors/multiplexers  
contains inverters and drivers to supply full binary  
decoding data selection to the AND-OR gates.  
Separate output control inputs are provided for  
each of the two four-line sections.  
17  
16  
15  
14  
2C3  
2G  
B
9 10 11 12 13  
The 3-state outputs can interface with and drive  
data lines of bus-organized systems. With all but  
one of the common outputs disabled (at a  
high-impedance state), the low-impedance of  
the single enabled output will drive the bus line  
to a high or low logic level. Each output has  
its own strobe (G). The outputs are disabled when  
G is high.  
NC − No internal connection  
logic symbol  
1
0
1
A
2
0
3
The 54ACT11253 is characterized for operation  
over the full military temperature range of − 55°C  
to 125°C. The 74ACT11253 is characterized for  
operation from − 40°C to 85°C.  
G
B
MUX  
6
1G  
EN  
0
16  
FUNCTION TABLE  
1C0  
15  
SELECT  
OUTPUT  
3
5
DATA INPUTS  
OUTPUT  
Y
1C1  
14  
1C2  
13  
1
2
3
1Y  
2Y  
INPUTS  
CONTROL  
G
B
X
L
A
X
L
C0 C1 C2 C3  
1C3  
7
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
2G  
11  
2C0  
10  
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
2C1  
9
L
H
X
X
X
X
H
L
2C2  
8
H
H
H
H
2C3  
L
H
X
X
H
L
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
H
H
H
H
Address inputs A and B are common to both sections.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢨ  
Copyright 1993, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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