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74ACQ241MSA PDF预览

74ACQ241MSA

更新时间: 2024-11-24 21:14:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 83K
描述
Bus Driver, AC Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, SSOP-20

74ACQ241MSA 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.73系列:AC
JESD-30 代码:R-PDSO-G20长度:7.2 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:2.05 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

74ACQ241MSA 数据手册

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January 1990  
Revised September 1998  
74ACQ241  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The ACQ241 is an octal buffer and line driver designed to  
be employed as a memory address driver, clock driver and  
bus oriented transmitter or receiver which provides  
improved PC board density. The ACQ utilizes Fairchild  
FACT Quiet Series technology to guarantee quiet output  
switching and improved dynamic threshold performance.  
FACT Quiet Series features GTO output control and  
undershoot corrector in addition to a split ground bus for  
superior performance.  
ICC and IOZ reduced by 50%  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch-up immunity  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Outputs source/sink 24 mA  
Faster prop delays than the standard AC  
Ordering Code:  
Order Number  
74ACQ241SC  
74ACQ241PC  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body  
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide  
N20A  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
IEEE/IEC  
Pin Names  
OE1, OE2  
Description  
3-STATE Output Enable Inputs  
Inputs  
I0–I7  
O0–O7  
Outputs  
Truth Tables  
Inputs  
Outputs  
OE1  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
L
H
Z
Connection Diagram  
Pin Assignment for DIP and SOIC  
H
Inputs  
Outputs  
OE2  
In  
(Pins 3, 5, 7, 9)  
H
H
H
L
H
X
L
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1998 Fairchild Semiconductor Corporation  
DS010642.prf  
www.fairchildsemi.com  

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