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74AC74TTR PDF预览

74AC74TTR

更新时间: 2024-09-14 04:28:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 86K
描述
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

74AC74TTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.06
Is Samacsys:N系列:AC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:90000000 Hz
最大I(ol):0.012 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V传播延迟(tpd):17.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:130 MHzBase Number Matches:1

74AC74TTR 数据手册

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74AC74  
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED:  
= 300MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74AC74B  
74AC74M  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
74AC74MTR  
74AC74TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 74  
IMPROVED LATCH-UP IMMUNITY  
transition of the clock pulse.  
CLEAR and PRESET are independent of the  
clock and accomplished by a low setting on the  
appropriate input.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74AC74 is an advanced high-speed CMOS  
DUAL D-TYPE FLIP FLOP WITH PRESET AND  
CLEAR fabricated with sub-micron silicon gate  
and double-layer metal wiring C MOS tecnology.  
A signal on the D INPUT is transferred to the Q  
and Q OUTPUTS during the positive going  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/12  

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