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74AC74

更新时间: 2024-09-09 22:53:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
6页 192K
描述
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

74AC74 数据手册

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DUAL D-TYPE POSITIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear  
and Set inputs and complementary (Q,Q) outputs. Information at the input is  
transferred to the outputs on the positive edge of the clock pulse. Clock triggering  
occurs at a voltage level of the clock pulse and is not directly related to the transition  
time of the positive-going pulse. After the Clock Pulse input threshold voltage has  
been passed, the Data input is locked out and information present will not be  
transferred to the outputs until the next rising edge of the Clock Pulse input.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
N SUFFIX  
CASE 646-06  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT74 Has TTL Compatible Inputs  
V
C
D
CP  
S
Q
Q
2
CC  
14  
D2  
13  
2
2
D2  
10  
2
12  
11  
9
8
C
S
D1  
D2  
D
Q
CP  
Q
1
1
2
2
2
PIN NAMES  
CP  
Q
D
Q
S
C
1
1
2
D SUFFIX  
CASE 751A-03  
PLASTIC  
D1  
D2  
D , D  
Data Inputs  
1
2
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
2
C
S
, C  
D1 D2  
1
2
3
CP  
4
5
6
7
, S  
D1 D2  
Q , Q , Q , Q  
C
D
S
Q
Q
1
GND  
1
1
2
2
D1  
1
1
D1  
1
LOGIC SYMBOL  
TRUTH TABLE (Each Half)  
Inputs  
CP  
Outputs  
Q
Q
1
1
S
C
D
Q
Q
S
C
D
D
D1  
D1  
D
CP  
1
1
L
H
L
H
H
H
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
L
L
H
H
L
H
H
H
H
L
X
Q
Q
0
0
Q
Q
2
CD  
2
S
D2  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
2
D
CP  
2
2
= LOW-to-HIGH Clock Transition  
Q (Q ) = Previous Q(Q) before  
0
0
LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  

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