74AC74

更新时间： 2024-11-18 22:53:11

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
9页	106K
描述
Dual D-Type Positive Edge-Triggered Flip-Flop

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AC74 数据手册

November 1988

Revised November 1999

74AC74 • 74ACT74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

Features

The AC/ACT74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at

a voltage level of the clock pulse and is not directly related

to the transition time of the positive-going pulse. After the

Clock Pulse input threshold voltage has been passed, the

Data input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

■ I_CCreduced by 50%

■ Output source/sink 24 mA

■ ACT74 has TTL-compatible inputs

Asynchronous Inputs:

LOW input to S_D(Set) sets Q to HIGH level

LOW input to C_D(Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C_Dand S_Dmakes both Q and Q

HIGH

Ordering Code:

Order Number Package Number

Package Description

74AC74SC

74AC74SJ

M14A

M14D

MTC14

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC74MTC

74AC74PC

74ACT74SC

74ACT74SJ

74ACT74MTC

74ACT74PC

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M14A

M14D

MTC14

N14A

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

D₁, D₂

CP₁, CP₂

_D1, C_D2

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

S_D1, S_D2

Q₁, Q₁, Q₂, Q₂

FACT is a trademark of Fairchild Semiconductor Corporation.

DS009920

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

下载PDF

与74AC74相关器件

型号	品牌	获取价格	描述	数据表
74AC74_05	FAIRCHILD	获取价格	Dual D-Type Positive Edge-Triggered Flip-Flop
74AC74B	STMICROELECTRONICS	获取价格	DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74AC74DCQR	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
74AC74FC	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
74AC74FCT	FAIRCHILD	获取价格	D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
74AC74M	STMICROELECTRONICS	获取价格	DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74AC74MTC	FAIRCHILD	获取价格	Dual D-Type Positive Edge-Triggered Flip-Flop
74AC74MTCX	FAIRCHILD	获取价格	Dual D-Type Flip-Flop
74AC74MTCX	ROCHESTER	获取价格	D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
74AC74MTCX_NL	FAIRCHILD	获取价格	Dual D-Type Positive Edge-Triggered Flip-Flop

与74AC74相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

22
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

14
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

44
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

43

产品中心

服务支持

精选活动

关于我们

帮助中心

74AC74

74AC74 数据手册

与74AC74相关器件

与74AC74相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74AC74

74AC74 数据手册

与74AC74相关器件

与74AC74相关文章

您还可以找

您在本页遇到什么问题？