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74AC521SCX_NL PDF预览

74AC521SCX_NL

更新时间: 2024-11-09 12:59:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 比较器
页数 文件大小 规格书
8页 83K
描述
Identity Comparator, AC Series, 8-Bit, Inverted Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20

74AC521SCX_NL 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.5Is Samacsys:N
其他特性:CASCADABLE系列:AC
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:IDENTITY COMPARATOR
湿度敏感等级:1位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3/5 V
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74AC521SCX_NL 数据手册

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November 1988  
Revised November 1999  
74AC521 74ACT521  
8-Bit Identity Comparator  
General Description  
Features  
The AC/ACT521 is an expandable 8-bit comparator. It  
compares two words of up to eight bits each and provides a  
LOW output when the two words match bit for bit. The  
expansion input IA = B also serves as an active LOW enable  
ICC reduced by 50%  
Compares two 8-bit words in 6.5 ns typ  
Expandable to any word length  
20-pin package  
input.  
Outputs source/sink 24 mA  
ACT521 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC521SC  
74AC521SJ  
74AC521PC  
74ACT521SC  
74ACT521SJ  
74ACT521PC  
M20B  
M20D  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering table.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Word A Inputs  
Word B Inputs  
A0A7  
B0B7  
TA = B  
OA = B  
Expansion or Enable Input  
Identity Output  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009964  
www.fairchildsemi.com  

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