74ABT377CMTC

更新时间： 2024-11-10 22:56:15

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器时钟
页数	文件大小	规格书
9页	104K
描述
Octal D-Type Flip-Flop with Clock Enable

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中文翻译

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数据手册

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74ABT377CMTC 数据手册

January 1993

Revised November 1999

74ABT377

Octal D-Type Flip-Flop with Clock Enable

General Description

Features

The ABT377 has eight edge-triggered, D-type flip-flops

with individual D inputs and Q outputs. The common buff-

ered Clock (CP) input loads all flip-flops simultaneously

when the Clock Enable (CE) is LOW.

■ Clock enable for address and data synchronization

applications

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

The CE input must be stable only one setup time prior to

the LOW-to-HIGH clock transition for predictable operation.

■ See ABT273 for master reset version

■ See ABT373 for transparent latch version

■ See ABT374 for 3-STATE version

■ Output sink capability of 64 mA, source capability

of 32 mA

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

■ Disable time less than enable time to avoid bus

contention

Ordering Code:

Order Number Package Number

Package Description

74ABT377CSC

74ABT377CSJ

74ABT377CMSA

74ABT377CMTC

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MSA20

MTC20

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Descriptions

Data Inputs

D₀–D₇

Clock Enable (Active LOW)

Clock Pulse Input

Q₀–Q₇

Data Outputs

Truth Table

Operating Mode

Inputs

Output

Q_n

D_n

Load “1”

Load “0”

Hold

No Change

(Do Nothing)

= HIGH Voltage Level

= Immaterial

= HIGH Voltage Level one setup time prior to the

LOW-to-HIGH Clock Transition

L = LOW Voltage Level

= LOW-to-HIGH Clock Transition

= LOW Voltage Level one setup time prior to the

LOW-to-HIGH Clock Transition

DS011550

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74ABT377CMTC相关器件

型号	品牌	获取价格	描述	数据表
74ABT377CMTCX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ABT377CSC	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ABT377CSCX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ABT377CSJ	FAIRCHILD	获取价格	Octal D-Type Flip-Flop with Clock Enable
74ABT377CSJC	TI	获取价格	ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, EIAJ TYPE2, PLASTIC,
74ABT377CSJX	FAIRCHILD	获取价格	Octal D-Type Flip-Flop
74ABT377D	NXP	获取价格	IC ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, FF/Latch
74ABT377DB	NXP	获取价格	IC ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, FF/Latch
74ABT377DB-T	ETC	获取价格	Octal D-Type Flip-Flop
74ABT377D-T	NXP	获取价格	IC ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, FF/Latch

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