Datasheet > 74LS74

74LS74

更新时间： 2024-01-13 06:57:12

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
6页	139K
描述
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

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技术参数
数据手册

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74LS74 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP14,.3	Reach Compliance Code：	compliant
风险等级：	5.92	JESD-30 代码：	R-PDIP-T14
JESD-609代码：	e0	逻辑集成电路类型：	D FLIP-FLOP
功能数量：	2	端子数量：	14
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP14,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
子类别：	FF/Latches	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
Base Number Matches：	1

74LS74 数据手册

June 1989

54LS74/DM54LS74A/DM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops

with Preset, Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered D flip-flops with complementary outputs. The informa-

tion on the D input is accepted by the flip-flops on the posi-

tive going edge of the clock pulse. The triggering occurs at a

voltage level and is not directly related to the transition time

of the rising edge of the clock. The data on the D input may

be changed while the clock is low or high without affecting

the outputs as long as the data setup and hold times are not

violated. A low logic level on the preset or clear inputs will

set or reset the outputs regardless of the logic levels of the

other inputs.

Features

Alternate military/aerospace device (54LS74) is avail-

able. Contact a National Semiconductor Sales Office/

Distributor for specifications.

Connection Diagram

Dual-In-Line Package

TL/F/6373–1

Order Number 54LS74DMQB, 54LS74FMQB, 54LS74LMQB,

DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN

See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table

Inputs

CLR

Outputs

CLK

High Logic Level

Either Low or High Logic Level

Low Logic Level

Positive-going Transition

This configuration is nonstable; that is, it will not persist when either the preset

and/or clear inputs return to their inactive (high) level.

The output logic level of Q before the indicated input conditions were established.

1995 National Semiconductor Corporation

TL/F/6373

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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