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74174

更新时间: 2024-11-11 22:40:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
4页 46K
描述
Hex/Quad D-Type Flip-Flop with Clear

74174 数据手册

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September 1986  
Revised February 2000  
DM74174  
Hex/Quad D-Type Flip-Flop with Clear  
General Description  
These positive-edge triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. All have a direct clear  
input.  
Features  
Contains six flip-flops with single-rail outputs  
Buffered clock and direct clear inputs  
Individual data input to each flip-flop  
Applications include:  
Information at the D inputs meeting the setup and hold time  
requirements is transferred to the Q outputs on the posi-  
tive-going edge of the clock pulse. Clock triggering occurs  
at a particular voltage level and is not directly related to the  
transition time of the positive-going pulse. When the clock  
input is at either the HIGH or LOW level, the D input signal  
has no effect at the output.  
Buffer/storage registers  
Shift registers  
Pattern generators  
Typical clock frequency 40 MHz  
Typical power dissipation per flip-flop 38 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74174  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
Function Table  
(Each Flip-Flop)  
Inputs  
Outputs  
Clear  
Clock  
D
X
H
L
Q
L
L
H
H
H
X
H
L
L
X
Q0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Don’t Care  
↑ = Transition from LOW-to-HIGH level  
Q
= The level of Q before the indicated steady-state input conditions were  
0
established.  
© 2000 Fairchild Semiconductor Corporation  
DS006557  
www.fairchildsemi.com  

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