73S8023C-DB

更新时间： 2024-02-28 10:25:52

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
19页	816K
描述
Demo Board User Manual

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技术参数
数据手册

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73S8023C-DB 技术参数

生命周期：	Transferred	包装说明：	5 X 5 MM, LEAD FREE, QFN-32
Reach Compliance Code：	unknown	风险等级：	5.59
Is Samacsys：	N	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-XQCC-N32	长度：	5 mm
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	0.9 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	5 mm
Base Number Matches：	1

73S8023C-DB 数据手册

73S8023C Demo Board User Manual

UM_8023C_027

Schematic/

Item

Silkscreen

Reference

Name

Function

Test Points:

TP1

Pin 18*

(VDDF_ADJ)

VDD voltage fault adjustment. The pin to the left is

connected to the VDDF_ADJ pin of the 73S8023C and

the pin to the right is GND. When either a resistor R3,

or a resistor network R1 and R3 is populated on the

board, it adjusts the VDD fault level that internally

triggers a card deactivation sequence.

By default, the resistors R1 and R3 are not connected.

This provides a VDD fault level of 2.3V typical (internally

set to the 73S8023C). Refer to the 73S8023C Data

Sheet for further information about VDD fault level and

determination of the resistor values.

*The silkscreen is in error. It is shown as ‘Pin 18’ when

actually it is Pin 17.

TP2

Factory Test

Factory test pin. Do not connect.

TP3

TP4

TP5

TP6

TP7

TP8

VCC

I/O

RST

CLK

2-pin test points for each respective smart card signal.

The pin label name is the respective signal (i.e. VCC,

CLK) and the 2nd pin is GND.

Figure 3: 73S8023C Demo Board Connectors, Jumpers and Test Points

Rev. 1.3

1...5 6 789 10 11...19

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73S8023C-IMR/F3	MAXIM	Analog Circuit, 1 Func, 5 X 5 MM, LEAD FREE, QFN-32	获取价格