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73S8009R-IMR/F PDF预览

73S8009R-IMR/F

更新时间: 2024-01-17 16:08:55
品牌 Logo 应用领域
TERIDIAN 模拟IC信号电路PC
页数 文件大小 规格书
23页 337K
描述
Low Cost Versatile Smart Card Interface

73S8009R-IMR/F 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:599351Samacsys Pin Count:21
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:QFN50P400X400X90-21NSamacsys Released Date:2017-01-11 21:24:41
Is Samacsys:N其他特性:ALSO OPERATES WITH 5 VOLT SUPPLY
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-XQCC-N20
长度:4 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

73S8009R-IMR/F 数据手册

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73S8009R Data Sheet  
DS_8009R_056  
Figures  
Figure 1: 73S8009R Block Diagram.........................................................................................................2  
Figure 2: 73S8009R 20-Pin QFN Pinout ..................................................................................................5  
Figure 3: 73S8009R 28-Pin SO Pinout.....................................................................................................5  
Figure 4: Typical 73S8009R Application Schematic ...............................................................................13  
Figure 5: Activation Sequence...............................................................................................................15  
Figure 6: Deactivation Sequence...........................................................................................................16  
Figure 7: OFF Activity Outside and Inside a Card Session .....................................................................17  
Figure 8: Power-down Operation ...........................................................................................................17  
Figure 9: CS Timing Definitions..............................................................................................................18  
Figure 10: I/O and I/OUC State Diagram................................................................................................19  
Figure 11: I/O to I/OUC Delay Timing Diagram.......................................................................................19  
Figure 12: 20-pin QFN Package Dimensions .........................................................................................20  
Figure 13: 28-Pin SO Package Dimensions ...........................................................................................21  
Tables  
Table 1: 73S8009R Pin Definitions ..........................................................................................................6  
Table 2: Absolute Maximum Device Ratings ............................................................................................8  
Table 3: Recommended Operating Conditions.........................................................................................8  
Table 4: DC Smart Card Interface Requirements .....................................................................................9  
Table 5: Digital Signals Characteristics ..................................................................................................11  
Table 6: DC Characteristics ...................................................................................................................11  
Table 7: Voltage / Temperature Fault Detection Circuits.........................................................................12  
Table 8: Choice of VCC Pin Capacitor ...................................................................................................15  
Table 9: Order Numbers and Packaging Marks......................................................................................22  
4
Rev. 1.3  

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