73K302L-IH

更新时间： 2024-01-14 22:52:00

品牌	Logo	应用领域
东电化 - TDK		调制解调器电信集成电路
页数	文件大小	规格书
29页	283K
描述
Single-Chip Modem

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技术参数
数据手册

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73K302L-IH 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.29	其他特性：	FULL DUPLEX
数据速率：	1.2 Mbps	JESD-30 代码：	R-PDIP-T28
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
最大压摆率：	12 mA	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子位置：	DUAL

73K302L-IH 数据手册

73K302L

Bell 212A, 103, 202

Single-Chip Modem

PARALLEL MICROPROCESSOR INTERFACE (continued)

NAME

PLCC/PIN

TYPE

DESCRIPTION

DIP NUMBER

Write. A low on this informs the 73K302L that data is available on

AD0-AD7 for writing into an internal register. Data is latched on the

rising edge of WR. No data is written unless both WR and the latched

CS are active low.

SERIAL MICROPROCESSOR INTERFACE

A0-A2

should be valid during any read or write operation.

DATA

I/O

Serial Control Data. Data for a read/write operation is clocked in or

out on the falling edge of the EXCLK pin. The direction of data flow is

controlled by the RD pin. RD low outputs data. RD high inputs data.

Read. A low on this input informs the 73K302L that data or status

information is being read by the processor. The falling edge of the RD

signal will initiate a read from the addressed register. The RD signal

must continue for eight falling edges of EXCLK in order to read all

eight bits of the referenced register. Read data is provided LSB first.

Data will not be output unless the RD signal is active.

Write. A low on this input informs the 73K302L that data or status

information has been shifted in through the DATA pin and is available

for writing to an internal register. The normal procedure for a write is

to shift in data LSB first on the DATA pin for eight consecutive falling

edges of EXCLK and then to pulse WR low. Data is written on the

rising edge of WR.

Note: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes the

data input and AD0, AD1 and AD2 become the address only. See the SERIAL CONTROL TIMING

diagram on page22

1 2 3 456 7 8...29

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