2.5 VOLT HIGH-SPEED TeraSync™ FIFO
*IDT72T1845, *IDT72T1855
*IDT72T1865, *IDT72T1875
*IDT72T1885, *IDT72T1895
IDT72T18105, IDT72T18115
IDT72T18125
18-BIT/9-BITCONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
*SPECIFIED PRODUCTS ARE EOL - LAST TIME BUY EXPIRES MAY 26, 2018
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
FEATURES:
• Choose among the following memory organizations:
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2,048 x 18/4,096 x 9
4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9
16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9
65,536 x 18/131,072 x 9
131,072 x 18/262,144 x 9
262,144 x 18/524,288 x 9
524,288 x 18/1,048,576 x 9
- x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information
• For IDT72T1845/55/65/75/85/95 functional replacement device use
IDT72T18125
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
FUNCTIONALBLOCKDIAGRAM
D0
-Dn
(x18 or x9)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
WRITE POINTER
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
BE
CONTROL
LOGIC
READ POINTER
IP
IW
BUS
CONFIGURATION
OW
RT
READ
CONTROL
LOGIC
MARK
ASYR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5909 drw01
Q0 -Qn (x18 or x9)
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2017
1
©
2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5909/20
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