Datasheet > 72841L10PF

72841L10PF

更新时间： 2022-12-01 20:35:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	339K
描述
TQFP-64, Tray

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数据手册

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72841L10PF 数据手册

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO^TM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

tRS

RSA (RSB)

tRSS

RSR

RENA1, RENA2

(RENB1, RENB2)

WENA1

(WENB1)

tRSR

(1)

WENA2/LDA

(WENB2/LDB)

tRSF

EFA, PAEA

(EFB, PAEB)

tRSF

FFA, PAFA

(FFB, PAFB)

tRSF

(2)

OEA (OEB) = 1

(QB

- QA

- QB8)

3034 drw 05

OEA (OEB) = 0

NOTES:

1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW

during reset will make the pin act as a load enable for the programmable flag offset registers.

2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.

3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.

Figure 4. Reset Timing

tCLK

tCLKH

tCLKL

WCLKA (WCLKB)

tDH

tDS

(DB

- DA

- DB8)

DATA IN VALID

ENH

ENS

WENA1

(WENB1)

NO OPERATION

tENS

WENA2 (WENB2)

(If Applicable)

WFF

tWFF

FFA

(FFB)

(1)

SKEW1

RCLKA (RCLKB)

RENA1, RENA2

(RENB1, RENB2)

3034 drw 06

NOTE:

1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between

the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.

Figure 5. Write Cycle Timing

MARCH 2013

1...6 7 8910 11 12...16

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