Datasheet > 72841L10PF

72841L10PF

更新时间： 2022-12-01 20:35:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	339K
描述
TQFP-64, Tray

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中文翻译

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数据手册

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72841L10PF 数据手册

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO^TM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

RCLKA (RCLKB)

tENS

tENH

RENA1, RENA2

(RENB1, RENB2)

NO OPERATION

tREF

EFA (EFB)

(QB

- QA

VALID DATA

- QB8)

tOLZ

tOHZ

tOE

OEA (OEB)

(1)

SKEW1

WCLKA (WCLKB)

WENA1 (WENB1)

WENA2 (WENB2)

3034 drw 07

NOTE:

1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time

between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)

Figure 6. Read Cycle Timing

WCLKA (WCLKB)

tDS

(DB

- DA

- DB8)

(First Valid Write)

tENS

WENA1 (WENB1)

tENS

WENA2 (WENB2)

(If Applicable)

(1)

tFRL

tSKEW1

RCLKA (RCLKB)

tREF

EFA (EFB)

tENS

RENA1, RENA2

(RENB1, RENB2)

(QB

- QA

- QB8)

tOLZ

tOE

OEA (OEB)

NOTE:

3034 drw 08

1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).

Figure 7. First Data Word Latency Timing

MARCH2013

1...7 8 91011 12 13...16

中文翻译

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