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7281L20PAG8 PDF预览

7281L20PAG8

更新时间： 2024-11-06 18:13:11
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片光电二极管
页数 文件大小 规格书
11页 143K
描述
FIFO, 1KX9, 20ns, Asynchronous, CMOS, PDSO56, TSSOP-56

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中文翻译

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7281L20PAG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.33
最长访问时间：20 ns其他特性：RETRANSMIT
周期时间：30 nsJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
内存密度：9216 bit内存宽度：9
湿度敏感等级：1功能数量：1
端子数量：56字数：1024 words
字数代码：1000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1KX9可输出：NO
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

7281L20PAG8 数据手册

 浏览型号7281L20PAG8的Datasheet PDF文件第2页浏览型号7281L20PAG8的Datasheet PDF文件第3页浏览型号7281L20PAG8的Datasheet PDF文件第4页浏览型号7281L20PAG8的Datasheet PDF文件第5页浏览型号7281L20PAG8的Datasheet PDF文件第6页浏览型号7281L20PAG8的Datasheet PDF文件第7页 
IDT7280  
IDT7281  
IDT7282  
IDT7283  
IDT7284  
IDT7285  
CMOS DUAL ASYNCHRONOUS FIFO  
DUAL 256 x 9, DUAL 512 x 9,  
DUAL 1,024 x 9, DUAL 2,048 x 9,  
DUAL 4,096 x 9, DUAL 8,192 x 9  
DESCRIPTION:  
FEATURES:  
TheIDT7280/7281/7282/7283/7284/7285aredual-FIFOmemoriesthat  
loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctional  
and compatible to two 7200/7201/7202/7203/7204/7205 FIFOs in a single  
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate  
pins. The devices use Full and Empty flags to prevent data overflow and  
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth  
word size and depth.  
•
•
•
•
•
•
•
The 7280 is equivalent to two 7200 256 x 9 FIFOs  
The 7281 is equivalent to two 7201 512 x 9 FIFOs  
The 7282 is equivalent to two 7202 1,024 x 9 FIFOs  
The 7283 is equivalent to two 7203 2,048 x 9 FIFOs  
The 7284 is equivalent to two 7204 4,096 x 9 FIFOs  
The 7285 is equivalent to two 7205 8,192 x 9 FIFOs  
Low power consumption  
The reads and writes are internally sequential through the use of ring  
pointers, with no address information required to load and unload data.  
Data is toggled in and out of the devices through the use of the Write (W)  
and Read (R) pins.  
— Active: 685 mW (max.)  
— Power-down: 83 mW (max.)  
Ultra high speed—12 ns access time  
Asynchronous and simultaneous read and write  
Offers optimal combination of data capacity, small foot print  
and functional flexibility  
Ideal for bi-directional, width expansion, depth expansion, bus-  
matching, and data sorting applications  
Status Flags: Empty, Half-Full, Full  
Auto-retransmit capability  
High-performance CMOS technology  
Space-saving TSSOP  
Industrial temperature range (–40oC to +85oC) is available  
•
•
•
The devices utilize a 9-bit wide data array to allow for control and parity  
bits at the user’s option. This feature is especially useful in data commu-  
nications applications where it is necessary to use a parity bit for transmis-  
sion/reception error checking. It also features a Retransmit (RT) capability  
that allows for reset of the read pointer to its initial position when RT is  
pulsedLOWtoallowforretransmissionfromthebeginningofdata.AHalf-Full  
Flagis available inthe single device mode andwidthexpansionmodes.  
These FIFOs are fabricated using IDT’s high-speed CMOS technology.  
They are designed for those applications requiring asynchronous and  
simultaneous read/writes in multiprocessing and rate buffer applications.  
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM  
DATA INPUTS  
DATA INPUTS  
(DA0-DA8)  
(DB0-DB8)  
RSA  
RSB  
WB  
WRITE  
CONTROL  
WRITE  
CONTROL  
RAM  
RAM  
WA  
ARRAY A  
256 x 9  
ARRAY B  
256 x 9  
512 x 9  
512 x 9  
1,024 x 9  
2,048 x 9  
4,096 x 9  
8,192 x 9  
1,024 x 9  
2,048 x 9  
4,096 x 9  
8,192 x 9  
WRITE  
POINTER  
WRITE  
POINTER  
READ  
POINTER  
READ  
POINTER  
THREE-  
STATE  
BUFFERS  
THREE-  
STATE  
BUFFERS  
READ  
CONTROL  
READ  
CONTROL  
RA  
RESET  
LOGIC  
RESET  
LOGIC  
FLAG  
LOGIC  
FLAG  
LOGIC  
EXPANSION  
LOGIC  
EXPANSION  
LOGIC  
XIA  
FFA EFA  
RB  
XIB  
XOA/HFA  
FLA/RTA  
FFB EFB  
FLB/RTB  
DATA  
OUTPUTS  
(QA0-QA8)  
XOB/HFB  
DATA  
OUTPUTS  
(QB0-QB8)  
3208 drw 01  
DECEMBER 1998  
1
1998 Integrated Device Technology, Inc.  
DSC-3208/3  
1234567...11

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