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723664L20PF PDF预览

723664L20PF

更新时间: 2024-11-14 19:46:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
37页 331K
描述
TQFP-128, Tray

723664L20PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:QFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:12 ns最大时钟频率 (fCLK):50 MHz
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
内存密度:294912 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36湿度敏感等级:3
端子数量:128字数:8192 words
字数代码:8000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX36封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified最大待机电流:0.001 A
子类别:FIFOs标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

723664L20PF 数据手册

 浏览型号723664L20PF的Datasheet PDF文件第2页浏览型号723664L20PF的Datasheet PDF文件第3页浏览型号723664L20PF的Datasheet PDF文件第4页浏览型号723664L20PF的Datasheet PDF文件第5页浏览型号723664L20PF的Datasheet PDF文件第6页浏览型号723664L20PF的Datasheet PDF文件第7页 
CMOS SyncBiFIFOTM  
WITH BUS-MATCHING  
2,048 x 36 x 2, 4,096 x 36 x 2,  
8,192 x 36 x 2  
PRELIMINARY  
IDT723654  
IDT723664  
IDT723674  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Big- or Little-Endian format for word and byte bus sizes  
Retransmit Capability  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
FEATURES:  
Memory storage capacity:  
IDT723654  
IDT723664  
IDT723674  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Clock frequencies up to 83 MHz (8ns access time)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRB flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has five  
default offsets (8, 16, 64, 256 and 1,024 )  
Serial or parallel programming of partial flags  
Auto power down minimizes power dissipation  
Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
Pincompatibletothelowerdensityparts, IDT723624/723634/723644  
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
FS2  
FS0/SD  
FS1/SEN  
A0-A35  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
B0-B35  
13  
Status Flag  
Logic  
EFA/ORA  
FFB/IRB  
AFB  
AEA  
36  
Read  
Write  
Pointer  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
SIZE  
MBF2  
5608 drw01  
TheSyncBiFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkoftheIntegratedDeviceTechnology,Inc.  
MARCH 2001  
COMMERCIAL TEMPERATURE RANGE  
1
2001 Integrated Device Technology, Inc.  
DSC-5608/3  

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