IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
FS1/SEN FlagOffset
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagoffsetregisterprogramming. DuringMasterReset,
FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
from Port A, and serial load.
Select1/
SerialEnable,
FS0/SD FlagOffset
Select0/
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenablesynchronousto
the LOW-to-HIGH transition of CLKA. When FS1/SEN isLOW, arisingedgeonCLKAloadthebitpresenton
FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32 for the
723624, 36 for the 723634, and 40 for the 723644. The first bit write stores the Y1 register MSB and the last bit
writestorestheX2registerLSB.
SerialData
MBA
MBB
MBF1
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs
are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2
outputregisterdataforoutput.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35 outputs
are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1
outputregisterdataforoutput.
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when
a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of
FIFO1.
MBF2
MRS1
Mail2Register
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writestothe mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
FIFO1Master
Reset
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePort B
outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialorparallel)
andoneofthreeprogrammableflagdefaultoffsetsforFIFO1andFIFO2.Italso configuresPortBforbussizeand
endianarrangement. FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
whileMRS1isLOW.
MRS2
FIFO2Master
Reset
I
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePort A
outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS2toggledsimultaneouslywithMRS1,selectsthe
programmingmethod(serialorparallel)andoneoftheprogrammableflagdefaultoffsetsforFIFO2.FourLOW-
to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccurwhileMRS2isLOW.
PRS1
PRS2
SIZE(1)
FIFO1Partial
Reset
I
I
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,program
mingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
FIFO2Partial
Reset
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,program
mingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
BusSizeSelect
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement
forPortB. ThelevelofSIZEmustbestaticthroughoutdeviceoperation.
(1)
SPM
SerialProgram-
mingMode
I
I
I
ALOWonthispinselectsserialprogrammingofpartialflagoffsets.AHIGHonthispinselectsparallel
programmingordefaultoffsets(8, 16, or64).
W/RA
W/RB
Port-AWrite/
ReadSelect
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to- HIGHtransitionof
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
Port-BWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to GND or VCC.
5
5秒后页面跳转
深入解析CS8416引脚说明、参数、技术特点
TPA3116D2功放芯片参数详解、引脚说明
移位寄存器74HC165引脚说明、驱动程序示例解读
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
