IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
I/O
Description
A0-A35
PortAData
36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
EmptyFlag
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2isless
thanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
AEB
PortBAlmost-
EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsinFIFO1isless
thanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
AFA
PortAAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsinFIFO1
islessthanorequaltothevalueintheAlmost-FullAOffsetregister, Y1.
AFB
PortBAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofemptylocationsinFIFO2
FIFO2islessthanorequaltothevalueintheAlmost-FullBOffsetregister, Y2.
B0-B35
PortAData
I/O
I
36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case,
depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data
flow)orwrittentoPortBfirst(B-to-A dataflow). ALOWonBEwillselectLittle-Endianoperation. Inthiscase,
the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first
(B-to-Adataflow). AfterMasterReset, thispinselectsthetimingmode. AHIGHonFWFTselectsIDT
Standardmode, aLOWselectsFirstWordFallThroughmode. Oncethetimingmodehasbeen
selected,thelevelonFWFTmustbestaticthroughoutdeviceoperation.
Fall Through
Select
BM(1)
Bus-Match
Select
(Port B)
I
I
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW
selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for
PortB. ThelevelofBMmustbestaticthroughoutdeviceoperation.
CLKA
CLKB
PortAClock
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincidenttoCLKB. FFA/IRA, EFA/ORA, AFA, andAEAareallsynchronizedtotheLOW-to-HIGHtransitionof
CLKA.
PortBClock
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincidenttoCLKA. FFB/IRB, EFB/ORB,AFB, andAEB aresynchronizedtotheLOW-to-HIGHtransitionof
CLKB.
CSA
CSB
Port A Chip
Select
I
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputsareinthehigh-impedancestatewhenCSAisHIGH.
Port B Chip
Select
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35
outputsareinthehigh-impedancestatewhenCSBisHIGH.
EFA/ORA PortAEmpty/
OutputReady
Flag
O
Thisisadualfunctionpin. IntheIDTStandardmode, the EFA functionisselected. EFA indicateswhetheror
nottheFIFO2memoryisempty. IntheFWFTmode, theORAfunctionisselected. ORAindicatesthepresence
ofvaliddataonA0-A35outputs, availableforreading. EFA/ORAissynchronizedtotheLOW-to-HIGH
transitionofCLKA.
EFB/ORB PortBEmpty/
OutputReady
Flag
O
Thisisadualfunctionpin. IntheIDTStandardmode, the EFB function isselected. EFB indicateswhetheror
nottheFIFO1memoryisempty.IntheFWFTmode,theORBfunctionisselected.ORBindicatesthepresence
ofvaliddataontheB0-B35outputs,availableforreading.EFB/ORBissynchronizedtotheLOW-to-HIGHtransition
ofCLKB.
ENA
Port A Enable
Port B Enable
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
ENB
FFA/IRA
Port A Full/
InputRead
Flag
O
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether or
nottheFIFO1memoryisfull. IntheFWFTmode, theIRAfunctionisselected. IRAindicateswhetherornot
there isspaceavailableforwritingtotheFIFO1memory. FFA/IRAissynchronizedtotheLOW-to-HIGH
transitionofCLKA.
FFB/IRB
Port B Full/
Input Ready
Flag
O
This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether or
not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not
there is space available for writing to the FIFO memory. FFB/IRB is synchronized to the LOW-to-HIGH transition
of CLKB.
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