Datasheet > 723624L12PF

723624L12PF

更新时间： 2024-02-20 03:37:18

品牌	Logo	应用领域
艾迪悌 - IDT		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
35页	514K
描述
Bi-Directional FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

723624L12PF 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP-128	针数：	128
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.52
最长访问时间：	8 ns	其他特性：	MAIL BOX
最大时钟频率 (fCLK)：	83 MHz	周期时间：	12 ns
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	9216 bit
内存集成电路类型：	BI-DIRECTIONAL FIFO	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	128	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256X36	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP128,.63X.87,20	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.001 A	子类别：	FIFOs
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

723624L12PF 数据手册

IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIALTEMPERATURERANGE

PINDESCRIPTIONS

Symbol

Name

I/O

Description

A0-A35

PortAData

36-bitbidirectionaldataportforsideA.

AEA

PortAAlmost-

EmptyFlag

ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2isless

thanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.

AEB

PortBAlmost-

EmptyFlag

ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsinFIFO1isless

thanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.

AFA

PortAAlmost-

Full Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsinFIFO1

islessthanorequaltothevalueintheAlmost-FullAOffsetregister, Y1.

AFB

PortBAlmost-

Full Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofemptylocationsinFIFO2

FIFO2islessthanorequaltothevalueintheAlmost-FullBOffsetregister, Y2.

B0-B35

PortAData

I/O

36-bitbidirectionaldataportforsideB.

BE/FWFT Big-Endian/

FirstWord

This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case,

depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data

flow)orwrittentoPortBfirst(B-to-A dataflow). ALOWonBEwillselectLittle-Endianoperation. Inthiscase,

the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first

(B-to-Adataflow). AfterMasterReset, thispinselectsthetimingmode. AHIGHonFWFTselectsIDT

Standardmode, aLOWselectsFirstWordFallThroughmode. Oncethetimingmodehasbeen

selected,thelevelonFWFTmustbestaticthroughoutdeviceoperation.

Fall Through

Select

BM⁽¹⁾

Bus-Match

Select

(Port B)

A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW

selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for

PortB. ThelevelofBMmustbestaticthroughoutdeviceoperation.

CLKA

CLKB

PortAClock

CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or

coincidenttoCLKB. FFA/IRA, EFA/ORA, AFA, andAEAareallsynchronizedtotheLOW-to-HIGHtransitionof

CLKA.

PortBClock

CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or

coincidenttoCLKA. FFB/IRB, EFB/ORB,AFB, andAEB aresynchronizedtotheLOW-to-HIGHtransitionof

CLKB.

CSA

CSB

Port A Chip

Select

CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

outputsareinthehigh-impedancestatewhenCSAisHIGH.

Port B Chip

Select

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35

outputsareinthehigh-impedancestatewhenCSBisHIGH.

EFA/ORA PortAEmpty/

OutputReady

Flag

Thisisadualfunctionpin. IntheIDTStandardmode, the EFA functionisselected. EFA indicateswhetheror

nottheFIFO2memoryisempty. IntheFWFTmode, theORAfunctionisselected. ORAindicatesthepresence

ofvaliddataonA0-A35outputs, availableforreading. EFA/ORAissynchronizedtotheLOW-to-HIGH

transitionofCLKA.

EFB/ORB PortBEmpty/

OutputReady

Flag

Thisisadualfunctionpin. IntheIDTStandardmode, the EFB function isselected. EFB indicateswhetheror

nottheFIFO1memoryisempty.IntheFWFTmode,theORBfunctionisselected.ORBindicatesthepresence

ofvaliddataontheB0-B35outputs,availableforreading.EFB/ORBissynchronizedtotheLOW-to-HIGHtransition

ofCLKB.

ENA

Port A Enable

Port B Enable

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.

ENB

FFA/IRA

Port A Full/

InputRead

Flag

This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether or

nottheFIFO1memoryisfull. IntheFWFTmode, theIRAfunctionisselected. IRAindicateswhetherornot

there isspaceavailableforwritingtotheFIFO1memory. FFA/IRAissynchronizedtotheLOW-to-HIGH

transitionofCLKA.

FFB/IRB

Port B Full/

Input Ready

Flag

This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether or

not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not

there is space available for writing to the FIFO memory. FFB/IRB is synchronized to the LOW-to-HIGH transition

of CLKB.

1 2 345 6 7...35

下载PDF

与723624L12PF相关器件

型号	品牌	描述	获取价格	数据表
723624L12PF8	IDT	Bi-Directional FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128	获取价格
723624L15PFG	IDT	CMOS SyncBiFIFO WITH BUS-MATCHING	获取价格
723624L15PFG8	IDT	CMOS SyncBiFIFO WITH BUS-MATCHING	获取价格
723624L20PF	IDT	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128	获取价格
723624L20PFI	IDT	Bi-Directional FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128	获取价格
723624L30PF	IDT	Bi-Directional FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP128	获取价格

与723624L12PF相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

723624L12PF

723624L12PF 技术参数

723624L12PF 数据手册

与723624L12PF相关器件

与723624L12PF相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

723624L12PF

723624L12PF 技术参数

723624L12PF 数据手册

与723624L12PF相关器件

与723624L12PF相关文章

您还可以找

您在本页遇到什么问题？