IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
D0–D8
MRS
Name
DataInputs
I/O
Description
I
I
Datainputs fora9-bitbus.
MasterReset
PartialReset
Retransmit
MRS initializes the readandwrite pointers tozeroandsets the outputregistertoallzeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program-
mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
RT
I
I
PRS initializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes. During
PartialReset, the existingmode (IDTorFWFT), programmingmethod(serialorparallel), and
programmableflagsettingsareallretained.
RT assertedonthe risingedge ofRCLKinitializes the READpointertozero, sets the EF flagto
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
ming method, existing timing mode or programmable flag settings. RT is useful to reread data from
the first physical location of the FIFO.
FWFT/SI
WCLK
FirstWordFall
Through/Serial In
I
I
DuringMasterReset, selects FirstWordFallThroughorIDTStandardmode. AfterMasterReset,
thispinfunctionsasaserialinputforloadingoffsetregisters
WriteClock
WhenenabledbyWEN, the risingedge ofWCLKwrites data intothe FIFOand offsets intothe
programmable registers forparallelprogramming, andwhenenabledbySEN, the risingedge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
WhenenabledbyREN, the risingedge ofRCLKreads data fromthe FIFOmemoryandoffsets from
theprogrammableregisters.
REN
OE
SEN
LD
ReadEnable
OutputEnable
SerialEnable
Load
I
I
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023 and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pinmustbe tiedtoeitherVCCorGNDandmustnottoggle afterMasterReset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF functionis selected. FF indicates whetherornotthe FIFO
memoryis full. Inthe FWFTmode, the IR functionis selected. IR indicates whetherornotthere is
spaceavailableforwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
Inthe IDTStandardmode, the EF functionis selected. EF indicates whetherornotthe FIFO
memoryis empty. InFWFTmode, the OR functionis selected. OR indicates whetherornotthere
isvaliddataavailableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOWifthe numberofwords inthe FIFOmemoryis more than totalwordcapacityofthe
FIFOminus thefulloffsetvaluem,whichis storedintheFullOffsetregister. Therearetwopossible
default values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAE goes LOWifthe numberofwords inthe FIFOmemoryis less thanoffsetn, whichis storedin
the EmptyOffsetregister. There are twopossible defaultvalues forn:127or1,023. Othervalues
forncanbe programmedintothe device.
HF
Q0–Q8
VCC
Half-FullFlag
DataOutputs
Power
O
O
HF indicates whethertheFIFOmemoryis moreorless thanhalf-full.
Dataoutputsfora9-bus
+5 Volt power supply pins.
GND
Ground
Groundpins.
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