IDT72261LA/72271LA SuperSyncFIFO™
16,384 x 9 and 32,768 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
canbeavoidedbycreatingcompositeflags,thatis,ANDingEFofeveryFIFO,
and separately ANDing FF of every FIFO. In FWFT mode, composite flags
canbecreatedbyORingORofeveryFIFO,andseparatelyORingIRofevery
FIFO.
Figure 21 demonstrates a width expansion using two IDT72261LA/
72271LAdevices. D0 -D8 fromeachdeviceforma18-bitwideinputbusand
Q0-Q8 from each device form a 18-bit wide output bus. Any word width can
beattainedbyaddingadditionalIDT72261LA/72271LAdevices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
The exceptions are the EF and FF functions in IDT Standard mode and the
IRandORfunctionsinFWFTmode. Becauseofvariationsinskewbetween
RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion
tovarybyonecyclebetweenFIFOs. InIDTStandardmode,suchproblems
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72261LA
72271LA
PROGRAMMABLE (PAE)
72261LA
72271LA
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4671 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
24