Datasheet > 72271

72271

更新时间： 2023-12-20 18:44:33

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
28页	531K
描述
32K x 9 SuperSync FIFO, 5.0V

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数据手册

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72271 数据手册

IDT72261LA/72271LA SuperSyncFIFO™

16,384 x 9 and 32,768 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKH

CLKL

WCLK

ENH

ENS

WEN

PAE

n words in FIFO ⁽²⁾

n+1 words in FIFO ⁽³⁾

n words in FIFO ⁽²⁾

n+1 words in FIFO ⁽³⁾

n+1 words in FIFO ⁽²⁾

n+2 words in FIFO ⁽³⁾

(4)

PAE

SKEW2

RCLK

REN

ENS

tENH

4671 drw 20

NOTES:

1. n = PAE offset.

2. For IDT Standard mode

3. For FWFT mode.

4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between

the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of WCLK only.

Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

tCLKH

tCLKL

WCLK

tENH

tENS

WEN

tHF

D/2 + 1 words in FIFO⁽¹⁾,

D/2 words in FIFO⁽¹⁾

D-1

D/2 words in FIFO⁽¹⁾

D-1

[

+ 2]

words in FIFO⁽²⁾

[

+ 1

]

words in FIFO⁽²⁾

[

+ 1

words in FIFO⁽²⁾

]

tHF

RCLK

tENS

REN

4671 drw 21

NOTES:

1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.

2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.

Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)

1...20 21 222324 25 26...28

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