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72245LB25JG8 PDF预览

72245LB25JG8

更新时间: 2024-11-15 00:43:31
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 338K
描述
CMOS SyncFIFO

72245LB25JG8 数据手册

 浏览型号72245LB25JG8的Datasheet PDF文件第2页浏览型号72245LB25JG8的Datasheet PDF文件第3页浏览型号72245LB25JG8的Datasheet PDF文件第4页浏览型号72245LB25JG8的Datasheet PDF文件第5页浏览型号72245LB25JG8的Datasheet PDF文件第6页浏览型号72245LB25JG8的Datasheet PDF文件第7页 
CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18, and 4,096 x 18  
IDT72205LB, IDT72215LB,  
IDT72225LB, IDT72235LB,  
IDT72245LB  
writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering  
needs, such as optical disk controllers, Local Area Networks (LANs), and  
interprocessorcommunication.  
FEATURES:  
256 x 18-bit organization array (IDT72205LB)  
512 x 18-bit organization array (IDT72215LB)  
1,024 x 18-bit organization array (IDT72225LB)  
2,048 x 18-bit organization array (IDT72235LB)  
4,096 x 18-bit organization array (IDT72245LB)  
10 ns read/write cycle time  
TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled  
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread  
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput  
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).  
Thereadclockcanbetiedtothewriteclockforsingleclockoperationorthe  
twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An  
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof  
theoutput.  
ThesynchronousFIFOshavetwofixedflags, Empty (EF)andFull(FF),  
andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The  
offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,  
andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable  
when the FIFO is used in a single device configuration.  
ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The  
XI and XO pins are used to expand the FIFOs. In depth expansion configu-  
ration, First Load (FL) is grounded on the first device and set to HIGH for all  
other devices in the Daisy Chain.  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated  
usinghigh-speedsubmicronCMOStechnology.  
Empy and Full flags signal FIFO status  
Easy expandable in depth and width  
Asynchronous or coincident read and write clocks  
Programmable Almost-Empty and Almost-Full flags with  
default settings  
Half-Full flag capability  
Dual-Port zero fall-through time architecture  
Output enable puts output data bus in high-impedence state  
High-performance submicron CMOS technology  
Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high  
speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
MARCH 2013  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2766/3  

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