CMOSSyncFIFO™
64 x 9, 256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72421,IDT72201
IDT72211,IDT72221
IDT72231,IDT72241
IDT72251
FEATURES:
DESCRIPTION:
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64 x 9-bit organization (IDT72421)
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1,024 x 9-bit organization (IDT72221)
2,048 x 9-bit organization (IDT72231)
4,096 x 9-bit organization (IDT72241)
8,192 x 9-bit organization (IDT72251)
10 ns read/write cycle time
Read and Write Clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set
to any depth
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048,4,096,and8,192x9-bitmemoryarray,respectively. TheseFIFOsare
applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea
networksandinterprocessorcommunication.
TheseFIFOshave9-bitinputandoutputports.Theinputportiscontrolled
byafree-runningclock(WCLK),andtwowriteenablepins(WEN1,WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when
thewriteenablepinsareasserted.Theoutputportiscontrolledbyanotherclock
pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can
betiedtotheWriteClockforsingleclockoperationorthetwoclockscanrun
asynchronousofoneanotherfordual-clockoperation.Anoutputenablepin
(OE) is provided on the read port for three-state control of the output.
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).
Twoprogrammableflags, Almost-Empty(PAE)andAlmost-Full(PAF), are
provided for improved system control. The programmable flags default to
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
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Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
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Output enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
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For through-hole product please see the IDT72420/72200/72210/ the load pin (LD).
72220/72230/72240 data sheet
TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnology.
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Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN1
WEN2
LD
OFFSET REGISTER
INPUT REGISTER
EF
FLAG
LOGIC
WRITE CONTROL
LOGIC
PAE
PAF
FF
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
2655 drw01
OE
Q0 - Q8
CIDTOandMtheMIDTElogRoaCrerIegAisteLredtrAadeNmaDrksofIInNtegrDateUdDSeviTceTRecIhnAoloLgy,InTc.TEheMSynPcFEIFORisaAreTgistUereRdtraEdemaRrkoAfInNtegGrateEdDSeviceTechnology,Inc.
AUGUST 2013
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2655/6
©
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