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72235LB25TF9 PDF预览

72235LB25TF9

更新时间: 2024-11-01 06:18:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 181K
描述
FIFO, 2KX18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64

72235LB25TF9 数据手册

 浏览型号72235LB25TF9的Datasheet PDF文件第2页浏览型号72235LB25TF9的Datasheet PDF文件第3页浏览型号72235LB25TF9的Datasheet PDF文件第4页浏览型号72235LB25TF9的Datasheet PDF文件第5页浏览型号72235LB25TF9的Datasheet PDF文件第6页浏览型号72235LB25TF9的Datasheet PDF文件第7页 
IDT72205LB  
IDT72215LB  
IDT72225LB  
IDT72235LB  
IDT72245LB  
CMOS SyncFIFO™  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18 and 4,096 x 18  
Integrated Device Technology, Inc.  
are applicable for a wide variety of data buffering needs, such  
as optical disk controllers, Local Area Networks (LANs), and  
interprocessor communication.  
FEATURES:  
• 256 x 18-bit organization array (IDT72205LB)  
• 512 x 18-bit organization array (IDT72215LB)  
• 1,024 x 18-bit organization array (IDT72225LB)  
• 2,048 x 18-bit organization array (IDT72235LB)  
• 4,096 x 18-bit organization array (IDT72245LB)  
• 10 ns read/write cycle time  
• Empty and Full flags signal FIFO status  
• Easily expandable in depth and width  
• Asynchronous or coincident read and write clocks  
• Programmable Almost-Empty and Almost-Full flags with  
default settings  
These FIFOs have 18-bit input and output ports. The input  
port is controlled by a free-running clock (WCLK), and an input  
enable pin (WEN). Data is read into the synchronous FIFO on  
everyclockwhenWEN isasserted.Theoutputportiscontrolled  
byanotherclockpin(RCLK)andanotherenablepin(REN).The  
read clock can be tied to the write clock for single clock  
operation or the two clocks can run asynchronous of one  
another for dual-clock operation. An Output Enable pin (OE) is  
provided on the read port for three-state control of the output.  
ThesynchronousFIFOshavetwofixedflags,Empty(EF)and  
Full (FF), and two programmable flags, Almost-Empty (PAE)  
and Almost-Full (PAF). The offset loading of the programmable  
flags is controlled by a simple state machine, and is initiated by  
asserting the Load pin (LD). A Half-Full flag (HF) is available  
when the FIFO is used in a single device configuration.  
These devices are depth expandable using a Daisy-Chain  
technique. The XI and XO pins are used to expand the FIFOs.  
In depth expansion configuration, FL is grounded on the first  
deviceandsettoHIGHforallotherdevicesintheDaisyChain.  
TheIDT72205LB/72215LB/72225LB/72235LB/72245LBis  
fabricated using IDT’s high-speed submicron CMOS technol-  
ogy.  
• Half-Full flag capability  
• Dual-Port zero fall-through time architecture  
• Output enable puts output data bus in high-impedance  
state  
• High-performance submicron CMOS technology  
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
• Industrial temperature range (–40°C to +85°C) is available  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB  
are very high-speed, low-power First-In, First-Out (FIFO)  
memories with clocked read and write controls. These FIFOs  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2000  
©2000 Integrated Device Technology, Inc.  
DSC-2766/-  
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  

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